1. Field of the Invention
The present invention relates to a structure and a method of fabricating a DRAM cell, or more in particular to a method of fabricating a memory cell of capacitor on bit-line type (COB) in which at least a bit line is formed first, and then at least a memory capacitor is formed on the bit line.
2. Description of the Related Art
The integration scale of semiconductor memory devices, especially, that of the dynamic RAM is ever on the increase every year. The resulting tendency is toward a further reduced area occupied by a unit memory element. A three-dimensional cell structure is therefore essential for securing a memory cell capacity sufficient for read and write operations (more than 20 fF). This has promoted general applications of cell structures using a trench-type capacitor and a stack-type capacitor.
A conventional method of fabricating a stack-type capacitor concerns a COB (capacitor over bit-line) memory cell as disclosed in, for example, "A CAPACITOR-OVER-BIT-LINE (COB) CELL WITH A HEMISPHERICAL-GRAIN STORAGE NODE FOR 64 Mb DRAMs', by M. Sakao et al., IEDM Technical Digest, pp.655-658, 1990.
This device will be described in detail below with reference to drawings.
FIG. 27 is a plan view showing a COB memory cell, FIG. 28 a perspective view taken diagonally from above the memory cell of FIG. 27, FIGS. 29, 30, 32 sectional views taken in line XXIX--XXIX in FIG. 27, showing semiconductor structures in the fabrication steps of the COB memory cell, and FIG. 31 a sectional view taken in line XXXI--XXXI in FIG. 27, showing a semiconductor structure in the fabrication step of the COB memory cell.
As shown in FIG. 29, first, an element-isolating oxide film 13 is formed on a silicon substrate 11 using the LOCOS process, while at the same time forming at least an element region 14. Next, a gate oxide film (not shown) is formed. Polysilicon gate electrodes 19 each having the upper surface and the sidewalls thereof covered with a silicon oxide film are formed on the gate oxide film. Contact holes are opened to the gate electrodes 19 in self-alignment on the element region 14, and a polysilicon film is deposited to form interconnects 50 (FIG. 29).
As shown in FIG. 30, a first interlayer insulating film 51 is deposited over the whole surface. The first interlayer insulating film 51 is patterned using a bit line contact pattern 52 thereby to form a bit line contact hole 53. Polysilicon 54 with impurities introduced therein is filled in the bit line contact hole 53. Then, a bit line 55 is formed using a tungsten polycide (FIG. 30).
As shown in FIG. 31, a second interlayer insulating film 56 is deposited over the whole surface of the bit line 55 and flattened. At least a storage node contact hole 57 is opened, thereby forming HSG (hemispherical grain) storage nodes 58 connecting to the interconnects 50 (FIG. 31).
As shown in FIG. 32, a capacitor insulating film (not shown) made of a silicon oxide thin film and a silicon nitride thin film is formed over the whole surface, followed by forming plate electrodes 59 by depositing polysilicon. Then, a third interlayer insulating film 60 is deposited on the whole surface thereby to form metal wires 61 (FIG. 32).
The DRAM memory cell fabricated using the prior art has the following problems:
(1) The interconnects 50 are inserted under the bit line 55, so that the height of the bit line contact 52 is increased, resulting in an increased aspect ratio. PA1 (2) The bit line contact 52 extends from the bit line to a diffusion layer, and therefore the aspect ratio of the bit line contact increases. PA1 (3) The interconnects 50 are formed in the vicinity of the bit line contact 62 of an adjacent element region. Therefore, the interconnects 50 are liable to short with the polysilicon 54 in the bit line contact by misregistration. PA1 (4) Since the bit line contact 52 is not formed in self-alignment with respect to the gate electrodes 19, a short is liable to occur between the bit line and the gate electrodes. PA1 (5) A new lithography process is required for forming the interconnects 50, leading to an increased number of fabrication steps.